View S30MS01GP25TAW002_665015.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

S30MS-P ORNANDTMFlash Family
S30MS01GP, S30MS512P
1Gb/512Mb, x8/x16, 1.8 Volt NAND Interface Memory Based on MirrorBitTM Technology
Data Sheet (Preliminary)
S30MS-P ORNANDTMFlash Family Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S30MS-P_00
Revision A
Amendment 7
Issue Date August 4, 2006
Data
Sheet
(Preliminary)
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content:
"This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice."
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
"This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications."
Combination
Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category:
"This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur."
Questions regarding these document designations may be directed to your local sales office.
ii
S30MS-P ORNANDTMFlash Family
S30MS-P_00_A7 August 4, 2006
S30MS-P ORNANDTM Flash Family
S30MS01GP, S30MS512P
1Gb/512Mb, x8/x16, 1.8 Volt NAND Interface Memory Based on MirrorBitTM Technology
Data Sheet (Preliminary)
Distinctive Characteristics
Single Power Supply Operation
- 1.8 volt read, erase, and program operations - VCC = 1.7 to 1.95V
Compatibility with NAND Flash I/O
- Provides pinout and command set compatibility with single-power supply NAND flash
Manufactured on 90 nm MirrorBitTM Process Technology Bus widths - x8 and x16 Page Size
- Full Page Read 2K + 64 Byte - Partial Page Read 512 + 16 Byte
High-Performance Cache Register
- Cache Register matches page size to improve programming throughput
100,000 Program/Erase Cycles per Sector Typical 10-Year Data Retention Typical Operating Temperature Ranges
- Wireless (-25C to +85C)
Block (erase unit) Architecture
- Number of Blocks 1Gb: 1K blocks 512Mb: 512 blocks - Block Size 128K + 4K Byte
Package options
- 48-pin TSOP - 137-ball FBGA MCP Compatible
100% Valid Blocks
Performance Characteristics
Read Access Times (Maximum) Full Page Random Access Partial Page Random Access Serial Read 25 s 8 s 25ns Read Current Erase Current Program Current Standby Current Current Consumption (typical) 40 mA 60 mA 60 mA 10 uA
Read, Program and Erase Performance (typical) x8 Program Erase Full Page Read Partial Page Read Legend: b = bit, B = Byte, K = 1024, M = 1048576 2.3 MB/s 2.7 MB/s 26.7 MB/s 24.3 MB/s x16 2.4 MB/s 2.7 MB/s 40.1 MB/s 34.9 MB/s
Publication Number S30MS-P_00
Revision A
Amendment 7
Issue Date August 4, 2006
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.
Data
Sheet
(Preliminary)
Contents
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. 2. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 137-Ball MS01GP MCP-Compatible FBGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 MS01GP and MS512P 48-Pin TSOP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 VBP137--137-Ball Fine Pitch Ball Grid Array (FBGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 48-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Names and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Capacitance (Ta = 25C, f = 1 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8 Program and Erase Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 12 13 13 14 14 15
3.
4.
5. 6. 7. 8.
9. 10. 11. 12.
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9.1 ID Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Schematic Cell Layout and Address Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10.1 Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operation Mode: Logic and Command Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 Page Duplicate Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 Write Operation Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7 Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 27 28 29 30 30 30 32
13.
Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 13.1 Power On/Off Sequence and Power-On Read Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 13.2 Status Read During a Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
14.
Tables
Table 9.1 Table 9.2 Table 9.3 ID Byte Settings Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4th ID Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 5th ID Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 10.5 Table 11.1 Table 11.2 Table 11.3 Table 12.1 Table 12.2
Memory Addressing Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 (1Gb) x 8 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 (512Mb) x8 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 (1Gb) x 16 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 (512) x 16 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Read Mode Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Page Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Status Output Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figures
Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Figure 9.7 Figure 9.8 Figure 9.9 Figure 9.10 Figure 9.11 Figure 9.12 Figure 9.13 Figure 10.1 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Figure 12.8 Figure 12.9 Figure 12.10 Figure 12.11 Figure 12.12 Figure 12.13 Figure 12.14 Figure 12.15 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Command Input Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Input Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Input Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Read Cycle Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Column Address Change in Read Cycle Timing Diagram (1/2). . . . . . . . . . . . . . . . . . . . . . . Column Address Change in Read Cycle Timing Diagram (2/2). . . . . . . . . . . . . . . . . . . . . . . Program Operation Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Erase Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Program Operation Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Duplicate Program Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Read Operation Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Column Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Input Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Duplicate Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page Duplicate Program Operation with Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Read Timing Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset (FFh) Command Input During Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset (FFh) Command Input During Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset (FFh) Command Input During a Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset (FFh) Command During Operations Other Than Program, Erase, or Read . . . . . . . . Status Read Command (70h) Input After a Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On/Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Auto-read Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Read During a Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RY/BY#: Termination for the Ready/Busy Pin (RY/BY#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . WP# Signal--Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16 16 17 17 18 18 19 19 20 20 21 21 23 26 27 28 28 29 30 30 30 31 31 32 32 32 32 33 33 34 34 35 36
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
3
Data
Sheet
(Preliminary)
1.
General Description
The S30MS-P is a 1.8V single voltage flash memory product manufactured using 90 nm MirrorBitTM technology. The S30MS01GP is a 1Gb device, organized as 64M Words or 128MB. The S30MS512P is a 512Mb device, organized as 32M Words or 64MB. The S30MS-P family of devices offer advantages such as: Fast write and sustained write speed suitable for data storage applications Fast read speed and reliability suitable for demanding code storage applications Proven MirrorBitTM technology The devices are offered in a 48-pin TSOP, or FBGA MCP-compatible packages. Each device has separate chip enable (CE#) controls for the FBGA package. The S30MS-P is a byte/word serial-type memory device that utilizes the I/O pins for both address and data input/output, as well as for command input. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state disks, pictures storage for still cameras, cellular phones, and other systems that require high-density non-volatile data storage. Typical application requirements are shown in the table below with reference to the ORNAND capabilities.
Application 2G Network 3G Network 3.5G Network (HSPDA) Full Speed USB MP3 Playback MPEG2 (H.262) MPEG4 (H.264) WiMax Minimum Requirements 14.4 Kbps (1.8 KB/sec) 2 Mbps (250 KB/sec) 2.5 MB/sec 1.5 MB/sec 320 Kbps (40 KB/sec) 3 MB/sec 1 MB/sec 0.25 MB/sec Spansion ORNAND
The devices include the following features: Automatic page 0 read, allows access of the data in page 0 without command and address input of read command after power-up Chip Enable Don't Care support for direct connection with microcontrollers Compatible with NAND Flash command set. Commands are written to the device using standard microprocessor write timing. Write cycles provide commands, addresses and data Initiation of program and erase functions through command sequences. Once a program or erase operation begins, the host system should only poll for status or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete Manufactured using MirrorBitTM flash technology resulting in the highest levels of quality, reliability, and cost effectiveness
4
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
2.
2.1
Connection Diagrams
137-Ball MS01GP MCP-Compatible FBGA Pinout
A1 RFU
A2 RFU
A3 RFU
A4 RFU
A5 RFU
A6 RFU
A7 RFU
A8 RFU
A9 RFU
A10 RFU
B1 RFU
B2 RFU
B3 RFU
B4 RFU
B5 RFU
B6 RFU
B7 RFU
B8 RFU
B9 DNU
B10 RFU
C1 RFU
C2 RFU
C3 VSS
C4 RFU
C5 RFU
C6 RFU
C7 N-PRE
C8 N-ALE
C9 N-CLE
C10 RFU
Legend
D1 RFU
D2 RFU
D3 RFU
D4 RFU
D5 RFU
D6 RFU
D7 RFU
D8 RFU
D9 N1-CE#
D10 RFU
RFU
E1 RFU
E2 RFU
E3 RFU
E4 RFU
E5 RFU
E6 DNU
E7 RFU
E8 RFU
E9 RFU
E10 RFU
Flash Shared
F1 RFU
F2 RFU
F3 RFU
F4 RFU
F5 RY/BY#
F6 RFU
F7 RFU
F8 RFU
F9 RFU
F10 RFU
ORNAND Flash
G1 RFU
G2 RFU
G3 RFU
G4 RFU
G6 RFU
G7 RFU
G8 RFU
G9 RFU
G10 RFU
Do Not Use
H1 RFU
H2 RFU
H3 VSS
H4 DQ1
H7 DQ6
H8 RFU
H9 RFU
H10 RFU
J1 RFU
J2 RFU
J3 RFU
J4 DQ9
J5 DQ3
J6 DQ4
J7 DQ13
J8 DQ15
J9 DNU
J10 RFU
K1 RFU L1 RFU
K2 DNU L2 N-VCC
K3 DQ0 L3 DQ8
K4 DQ10 L4 DQ2
K5 RFU L5 DQ11
K6 N-VCC L6 RFU
K7 DQ12 L7 DQ5
K8 DQ7 L8 DQ14
K9 VSS L9 N-WP#
K10 RFU L10 RFU
M1 RFU N1 N-WE# P1 RFU
M2 RFU N2 RFU P2 RFU
M3 RFU N3 RFU P3 RFU
M4 VSS N4 RFU P4 RFU
M5 RFU N5 RFU P5 RFU
M6 N2-CE# N6 RFU P6 RFU
M7 DNU N7 RFU P7 RFU
M8 RFU N8 RFU P8 RFU
M9 RFU N9 RFU P9 DNU
M10 RFU N10 N-RE# P10 RFU
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
5
Data
Sheet
(Preliminary)
2.2
MS01GP and MS512P 48-Pin TSOP Pinout
TSOP-48 X16
N.C N.C N.C N.C N.C N.C RY/BY# RE# CE# N.C N.C VCC VSS N.C N.C CLE ALE WE# WP# N.C N.C N.C N.C N.C
X8
N.C N.C N.C N.C N.C N.C RY/BY# RE# CE# N.C N.C VCC VSS N.C N.C CLE ALE WE# WP# N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
X8
N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C PRE VCC VSS N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C
X16
VSS I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 N.C PRE VCC N.C N.C N.C I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 VSS
6
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
3.
3.1
Physical Dimensions
VBP137--137-Ball Fine Pitch Ball Grid Array (FBGA)
D
0.15 C (2X)
10 9 8 7 6 5 4 3 2 1
A
e
D1
SE 7 E1
E e
P
NM
LK
J
HGF
E
DCB
A
PIN A1 CORNER
9 INDEX MARK
B
7
PIN A1 CORNER
TOP VIEW
0.15 C (2X)
SD
BOTTOM VIEW A A2 A1
6
0.10 C
SIDE VIEW b
M CAB MC
C
0.08 C
137X
0.15 0.08
NOTES: PACKAGE JEDEC VBP 137 N/A 13.00 mm x 11.00 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N b e SD / SE 0.35 MIN --0.17 0.60 NOM ------13.00 BSC. 11.00 BSC. 10.40 BSC. 7.20 BSC. 14 10 137 0.40 0.80 BSC. 0.40 BSC. G5,H5,H6 0.45 MAX 1.00 --0.76 NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 6 7 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3549 \ 16-038.25 \ 2.16.6
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
7
Data
Sheet
(Preliminary)
3.2
48-Pin TSOP
2X STANDARD PIN OUT (TOP VIEW) 2
1 N
0.10
2X (N/2 TIPS)
2X 0.10 A2
0.10 REVERSE PIN OUT (TOP VIEW) 3
1 N
A
SEE DETAIL B
B
E5
N 2
N +1 2
e 9 A1 C SEATING PLANE
0.08MM (0.0031") M C A-B S
N 2 N +1 2
D1 D 0.25
2X (N/2 TIPS)
5 4
B
A
B
SEE DETAIL A
b
6
7 WITH PLATING
7
(c)
c1
b1 SECTION B-B
R (c)
GAUGE PLANE
BASE METAL
e/2
PARALLEL TO SEATING PLANE
C
0.25MM (0.0098") BSC
X X = A OR B
L
DETAIL A
DETAIL B
Package Jedec Symbol A A1 A2 b1 b c1 c D D1 E e L 0 R N MIN
TS/TSR 048 MO-142 (D) DD MAX 1.20 0.15 0.05 1.00 0.95 1.05 0.20 0.23 0.17 0.22 0.17 0.27 0.10 0.16 0.10 0.21 19.80 20.00 20.20 18.30 18.40 18.50 11.90 12.00 12.10 0.50 BASIC 0.50 0.70 0.60 0 8 0.08 0.20 48 NOM
NOTES:
1 2 3 4
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982) PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP). PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15mm (.0059") PER SIDE. DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028"). THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND 0.25MM (0.0098") FROM THE LEAD TIP. LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
3355 \ 16-038.10c
5 6
7 8 9
8
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
4.
4.1
Pin Names and Descriptions
Pin Names and Functions
Pin Name I/O0 to I/O15 CLE ALE CE#, CE1#, CE2# RE# WE# WP# PRE RY/BY# VCC VSS N.C. Pin Function Data Input/Output Command Latch Enable Address Latch Enable Chip Enable Read Enable Write Enable Write Protect Power on Read Enable Ready/Busy Output Power Ground No Connection
4.2
Pin Descriptions
The device is a byte/word serial access memory that utilizes time-sharing input of address information. The device pin-outs are configured as shown in 137-Ball MS01GP MCP-Compatible FBGA Pinout on page 5.
Pin CLE Description Command Latch Enable: The CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the WE# signal while CE# is low and CLE is High. Address Latch Enable: The ALE signal is used to control loading of either address information or input data into the internal address/data register. Address information is latched on the rising edge of WE# if CE# is low and ALE is High. Input data is latched if CE# is low and ALE is Low. Chip Enable: The device enters a low-power Standby mode when the device is in Ready mode. The CE# signal is ignored when the device is in a Busy state (RY/BY# = L), such as during a Page Buffer Load or Erase operation, and will not enter Standby mode even if the CE# input goes high. The CE# signal may be inactive during the Page Buffer write and Page Buffer load of the array data. The 2Gb device has two chip enable pins: CE1# and CE2# (one per die). Write Enable: The WE# signal is used to control the acquisition of data from the I/O port. Read Enable: The RE# signal controls serial data output. Data is available tREA after the falling edge of RE#. The internal column address counter is also incremented (Address = Address + 1) on this falling edge. I/O Port: The I/O0 to I/O7 pins are used as a port for transferring address, command, and input/output data to and from the device. I/O Port: The I/O8 to I/O15 pins are used as a port for transferring input/output data to and from the device in x16 mode only. I/O8 to I/O15 pins must be low level during address and command input. Write Protect: The WP# signal is used to protect the device from accidental programming or erasing. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. Ready/Busy:The RY/BY# output signal is used to indicate the operating condition of the device. The RY/BY# signal is in Busy state (RY/BY# = L) during the Program, Erase, and Read operations and return to Ready state (RY/BY# = H) after completion of the operation. The output buffer for this signal is an open drain. Power-on Read Enable: The PRE controls auto read operation executed during power-on. The power-on autoread is enabled when PRE pin in tied to VCC. Ground: VSS is the Ground. No Connection: Lead is not internally connected.
ALE
CE#, CE1#, CE2#
WE# RE# I/O0 to I/O7 I/O8 to I/O15 WP#
RY/BY#
PRE VSS N.C
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
9
Data
Sheet
(Preliminary)
5.
Block Diagram
VCC VSS X-Decoder RY/BY# 2Gb: (2048M + 64M) bit 1Gb: (1024M + 32M) bit 512 Mb: (512M + 16M) bit Flash Array
Address Register & Decoders
Data Register & S/A Cache Register Y-Decoder
Command Command Register I/O Buffers & Latches VCC VSS I/00
CE# RE# WE#
Control Logic & High Voltage Generator
Global Buffers
Output Driver
I/O7 or I/O15 CLE ALE PRE WP#
6. Absolute Maximum Ratings
Parameter Voltage on any pin relative to Vss Storage Temperature Operating Temperature Temperature under bias Short circuit current Symbol VIN/OUT VCC TSTG TOPR TBIAS IOS Rating -0.5 to Vcc + 0.5 V -0.5 to + 2.5 -65 to +150 0 to +70 (Commercial) -40 to +85 (Industrial) -25 to +85 (Wireless) -65 to 125 5
o o
Unit
C C C
o
mA
Notes: 1. Minimum DC voltage is -0.6v on input/output pins. During transitions, this level may undershoot to -2.0v for periods <30ns. 2. Maximum DC voltage on input/output pins is Vcc+0.3v which, during transitions, may overshoot to Vcc+2.0v for periods < 20ns. 3. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as details in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
10
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
7.
Ordering Information
The order number is formed by a valid combinations of the following:
S30MS
01G
P
25
B
F
W
00
2 Packing Type 0 = Tray 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel Model Number (3) (4) 00 = x8; ECC-Free 01 = x16; ECC-Free 50 = x8; ECC-Required with Boot Block 51 = x16; ECC-Required with Boot Block Temperature Range W = Wireless (-25C to +85C) Package Material Set A = Standard F = Pb-Free Package Type T = Thin Small Outline Package B = Ball-Grid Array Package Speed Option Serial Read Access Time 25 = 25 ns Process Technology P = 90 nm MirrorBitTM Technology Flash Density 01G= 1Gb 512= 512Mb Product Family S30MS = 1.8 volt -only, NAND Interface Flash Memory
7.1
Valid Combinations
Valid Combination list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Valid Combinations Base Ordering Part Number S30MS01GP S30MS512P Speed Option 25 TAW, TFW Package Type, Material, and Temperature Range BAW, BFW Model Number 00, 01, 50, 51 Packing Type 0, 3 (Note 1) Package Type 137-Ball FBGA TSOP-48
Notes: 1. Type 0 is standard. Specify other options as required. 2. See the MCP ORNAND data sheet for further package details. 3. Model Numbers 50 and 51 must use 2-bit detection, 1-bit correction for applications that require 100% error-free read performance. 4. Model Numbers 50 and 51 may have up to 2% invalid blocks. 5. Model Numbers 50 and 51 have a boot block (Block 0 is valid upon shipment and error-free through 1000 cycles).
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
11
Data
Sheet
(Preliminary)
8.
8.1
Electrical Specifications
Absolute Maximum Ratings
Parameter Voltage on any pin relative to Vss Storage Temperature Operating Temperature Temperature under bias Short circuit current Symbol VIN/OUT VCC TSTG TOPR TBIAS IOS Rating -0.5 to VCC + 0.5 -0.5 to + 2.5 -65 to +150 -25 to +85 (Wireless) -65 to +125 5 C C C mA Unit V
Notes: 1. Minimum DC voltage is -0.6 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods <30 ns. 2. Maximum DC voltage on input/output pins is VCC +0.3 V which, during transitions, may overshoot to VCC+2.0 V for periods < 20 ns. 3. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
8.2
Capacitance (Ta = 25C, f = 1 MHz)
Parameter Symbol CIN CIN2 CIN3 COUT Parameter Description Input Capacitance CE# pin Input Capacitance WE# pin Input Capacitance Output Capacitance Test Condition VIN = 0 VIN = 0 VIN = 0 VOUT = 0 Typ. -- -- -- -- -- -- Max. 10 10 17 32 10 10 Unit pF pF pF pF pF pF
Notes: 1. Test conditions Ta = 25C, f = 1.0 MHz 2. Sampled, not 100% tested.
8.3
Valid Blocks
Valid Blocks are fully erased when the device is shipped from the factory. To identify blocks that are invalid at the time of shipment, the system must read the lowest address in the first two pages of the spare area. If a non-blank data pattern is read from either of these two addresses, the block is invalid.
Parameter Symbol Parameter Description
Density 512Mb
Model Number 50, 51 00, 01
Min. 502 512 1004 1024
Max. 512 512 1024 1024
Unit Blocks Blocks Blocks Blocks
NVB
Number of Valid Blocks 50, 51 1Gb 00, 01
12
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
8.4
Recommended DC Operating Conditions
Parameter Symbol VCC VSS Parameter Description Power Supply Voltage Power Supply Voltage Min. 1.7 0 Typ. 1.8 0 Max. 1.95 0 Unit V V
8.5
DC Characteristics
Parameter Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ISB1 Parameter Description VCC active read current (average during read cycle) VCC current during data transfer from memory cell array to Page Buffer VCC current during data output Program current (standard mode) Erase Current (standard mode) Stand-by Current (TTL) Test Conditions tRC = 25 ns, IOUT = 0 mA -- tRC = 25 ns -- -- CE# = VIH, WP# = PRE# = VIL CE# = VCC -0.2 V, WP# = PRE# = 0.2 V All other pins = -0.1 V VIN = 0 to VCC, VCC= VCC max VOUT = 0 to VCC, VCC= VCC max Min. -- -- -- -- -- -- Typ. 40 40 10 60 60 -- Max. 45 45 20 75 75 1 Unit mA mA mA mA mA mA
ISB2
Stand-by Current (CMOS)
--
10
60
A
ILI ILO VIH (note 1) VIL (note 2) VOH VOL IOL
Input Leakage Current
--
--
1
A
Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level
-- VCC - 0.4
-- -- -- --
1 VCC + 0.2 0.4 --
A V V V
-- IOH = -100 A, VCC= VCCmin IOL = 100 A, VCC= VCC min VOL = 0.1 V
-0.3 VCC - 0.1 --
Output Low Voltage Level Output Low Current (RY/BY#)
--
0.1
V
2
4
--
mA
Notes: 1. VIH can overshoot to VCC +0.4 V for durations of 20 ns or less. 2. VIL can undershoot to -0.4 V for durations of 20 ns or less.
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
13
Data
Sheet
(Preliminary)
8.6
AC Characteristics
Parameter Symbols tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tWW tRR tRW tRP tRC tREA tCR tAR tCLR tOH tRHZ tCHZ tREH tIR tRHW tWHC tWHR tR tRPRE tWB tRST CLE Setup Time CLE Hold Time CE# Setup Time CE# Hold Time Write Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE# High Hold Time WP# High to WE# Low Ready to RE# Falling Edge Ready to WE# Falling Edge Read Pulse Width Read Cycle Time RE# Access Time CE# to RE# Time ALE to RE# Time CLE to RE# Time Data Output Hold Time RE# High to Output High Impedance CE# High to Output High Impedance RE# High Hold Time Output High Impedance to RE# Falling Edge RE# High to WE# Low WE# High to CE# Low WE# High to RE# Low Full Page Data Transfer from Memory Cell Array to Register Partial Page Data Transfer from Memory Cell Array to Register Full page Data Transfer to Register During Power On Read WE# High to Busy Device Resetting Time (Read/Program/Erase) Description Min. -1 8 0 8 25 -1 8 15 8 40 10 100 20 20 17 25 -- 10 10 10 5 -- -- 8 0 30 30 60 -- -- -- -- -- -- 15 15 -- -- -- -- -- 25 s 8 50 100 1/1/15 s ns s Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 17 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
8.7
AC Test Conditions
Operating Range Input level Input comparison level Output data comparison level Load capacitance (CL) Transition time (tT) (input rise and fall times) VCC 1.7 V to 1.95 V 0.0 to VCC VCC/2 VCC/2 30 pF 5 ns
14
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
8.8
Program and Erase Characteristics
Symbol tCBSY1 tCBSY2 tPROG tPPROG N tBERASE Parameter Dummy Busy Time for Cache Programming (first 15h) (Note 2) Dummy Busy Time for Cache Programming (next 15h) (Note 3) Page Programming Time Partial Page Programming Time Number of Programming Cycles on Same Page (Note 1) Block Erasing Time Min. -- -- -- -- -- -- Typ. (Note 4) 0.4 0.8 0.8 260 -- 50 Max. (Note 5) 0.8 4.4 4.4 1400 8 150 ms Unit s ms ms s
Notes: 1. One programming cycle per segment. Refer to Page Program on page 27 for more information. 2. First cache programming of a sequence. 3. Following cache programming of a sequence - second page and following pages. 4. Typical program and erase times assume the following conditions: 25C, 1.8 V VCC, 10,000 cycles; checkerboard data pattern. 5. Under worst case conditions of 90C, VCC=1.70 V, 100,000 cycles.
9. Timing Diagrams
Figure 9.1 Command Input Cycle Timing Diagram
CLE tCLS tCS CE# tWP WE# tALS tALH tCLH tCH
ALE tDS I/O : VIL or VIH tDH
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
15
Data
Sheet
(Preliminary)
Figure 9.2 Address Input Cycle Timing Diagram
tCLH CLE tWC tCH CE# tWP tWH tCS tCLS
WE# tALH tALS
ALE tDS tDH
I/O
Col. Add1
Col. Add2
Row Add1
Row Add2 : VIH or VIL
Figure 9.3 Data Input Cycle Timing Diagram
tCLH CLE tCH tCS tCLS
CE# tWC tALH tALS
ALE tWP WE# tDS tDH tWH
I/O
D IN0
D IN1
D IN 2111 (x8) 1055 (x16) : VIH or VIL
16
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
Figure 9.4 Serial Read Cycle Timing Diagram
tRC CE# ALE# CE# don't care tCH
tCR
tOH
CLE#
tRP tREH
RE#
tREA tOH
I/Ox
tRR
tCHZ
Dout0
tRHZ
Dout1
DoutN
Figure 9.5 Status Read Cycle Timing Diagram
CLE tCS tCH tWHC tWHR RE# tDS t DH 70H tIR tREA tOH tCHZ Status Output tRHZ RY/BY# : VIH or VIL tCLR tCLS tCLH
CE#
tWP WE#
tCR tOH
I/Ox
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
17
Data
Sheet
(Preliminary)
Figure 9.6 Read Cycle Timing Diagram
tCLR
CLE
tCLS tCS
tCLH tCH
CE# tWC WE# tALH tALS tALH tALS tAR ALE tR t WB t DS t DH I/O 00h Col. Add1 Col. Add2 Row Add1 Row Add2 30h t RR t REA DOUT A DOUT A+1 t RC tCR
RE#
RY/BY#
Column Address A
Page Address P
Data out from Col. Add. A
Figure 9.7 Column Address Change in Read Cycle Timing Diagram (1/2)
CLE tCLR tCLS tCS CE# tWC WE# tALH tALS tALH
tALS
tCLH tCH
tCR
tAR
ALE tR RE# tDS tDH Col. Add1 Col. Add2 Row Add1 Row Add2 tRR 30h tWB tREA D OUT A D OUT A+1 D OUT A+N tRC
I/O
00h
Column address A RY/BY#
Page address P
Page address P
Column address A Part A A
Part B
18
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
Figure 9.8 Column Address Change in Read Cycle Timing Diagram (2/2)
CLE tCLR tCLS tCS CE# tRHW WE# tALH tALS tALH tALS tWC tCR tCLH tCH
ALE tRC RE# tDS tDH tIR I/O D OUT A +N 05h Col. Add1 Col. Add2 E0h D OUT B D OUT B+1 D OUT B+N' tREA
RY/BY# Part A A Part B
Column address B
Page address P
Column address B
Figure 9.9 Program Operation Timing Diagram
tCLS CLE tCLS tCLH tCS CE# tCH WE# tCS
tALH tALS
tALH tALS tPROG tWB tRW
ALE
RE# tDS I/O tDH tDS t DH Col. Add1 Col. Add2 Row Row Add1 Add2 Page Address P D IN0 A D IN1 D IN 10h 70h Status output
80h
Column Address A RY/BY#
2111 (x8) 1055 (x16)
: VIH or VIL
: Do not input data while data is being output.
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
19
Data
Sheet
(Preliminary)
Figure 9.10 Block Erase Timing Diagram
CLE tCLS tCS tCLH tCLS
CE#
WE# tALH
tALS ALE
tWB
tBERASE
RE#
tDS tDH 60h Row Add1 Note 2 Busy Row Add2 D0h 70h Status output Note 1
I/O
RY/BY#
Auto Block Erase Setup command : VIH or VIL
Erase S tart command
Read Status command
: Do not input da while data is being output. ta
Notes: 1. If I/O 0 = 0, then the erase is successful. If I/O0 = 1, then there is an error in the erase. 2. Only the block address part of the Row Address bytes are used; page address is ignored.
Figure 9.11 Cache Program Operation Timing Diagram
CLE
C E# tWC
W E# tWB
tC BSY
tWB
tCBSY2
ALE
R E#
I/O x
80h Serial Data
Col Add1 Col Add2
Row Add1 Row Add2
Din N
Din M
15h P rogram C ommand (Dummy)
80h
Col Add1 Col Add2
Row Add1 Row Add2
Din N
Input Command RY /BY# Column Address Page Address
Serial Input
Din 10h M P rogram C onfirm C ommand (True)
70h
I/O
Column Address Page Address

Note: CE#, CLE, and ALE are Don't care.
20
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
Figure 9.12 Page Duplicate Program Timing Diagram
CLE
C E# tW C W E# tW B tP R O G tW B ALE
R E# tR I/O x 00h Col Add1 Col Add2 Row Add1 Row Add2 C olumn Address R Y/ BY# B us y Page Duplicate Date Input C ommand B us y I/O 0=0 Successful P rogram I/O 0=1 E rror in P rogram Page Address 35h 85h Col Add1 Col Add2 Row Add1 Row Add2 C olumn Address Page Address Data 1 Data N 10h 70h I/O0
R ead Status C ommand
Note: CE#, CLE, and ALE are Don't care.
9.1
ID Read
Figure 9.13 ID Read Operation Timing Diagram
CLE tCS CE# tCS WE# tALH ALE tALS tALH tCR tAR tCLS tCH tCLS
tCH
RE#
tDS tDH
I/O
90h
00h tREA Address Input
01h
2nd byte
3rd byte
4th byte
5th byte
Maker Code
Device Code
: VIH or VIL
Note: CE#, CLE, and ALE are Don't care.
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
21
Data
Sheet
(Preliminary)
Table 9.1 ID Byte Settings Summary
Byte 1st Byte Maker Code 512 Mb (x8) 512 Mb (x16) 2nd Byte Device Code 1st Byte 1 Gb (x8) 1 Gb (x16) Model Numbers 50 and 51 (ECC Required) 3rd Byte 4th Byte 5th Byte Note: In x16, I/O15 - I/O8 = 00h Device Code 2nd Byte Model Numbers 00 and 01 Block Size, Simultaneous Programmed Pages, RFU Page Size, Spare Size, RFU 01h 00h 22h A1h B1h 00h Description Hex Data 01h 81h 91h
Table 9.2 4th ID Byte
Description Block Size: 128 KBytes Block Size: 512 KBytes Block Size: 2048 KBytes 1 2 Number of simultaneously programmed pages 4 8 X X X X X X 1 1 0 1 X X X X X X I/O7 X X X X X I/O6 X X X X X I/O5 X X X X X I/O4 X X X 0 0 I/O3 X X X 0 1 I/O2 0 0 0 X X I/O1 0 0 1 X X I/O0 0 1 0 X X
Table 9.3 5th ID Byte
Description Page Size: 512 KBytes Page Size: 1024 KBytes Page Size: 2048 KBytes Page Size: 4096 KBytes Page Size: 8192 KBytes Spare Size: 0 Bytes Spare Size: 8 Bytes Spare Size: 16 Bytes Spare Size: 32 Bytes Spare Size: 64 Bytes I/O7 X X X X X X X X X X I/O6 X X X X X X X X X X I/O5 X X X X X 0 0 0 0 1 I/O4 X X X X X 0 0 1 1 0 I/O3 X X X X X 0 1 0 1 0 I/O2 0 0 0 0 1 X X X X X I/O1 0 0 1 1 0 X X X X X I/O0 0 1 0 1 0 X X X X X
22
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
10. Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
10.1
Array Organization
Figure 10.1 Array Organization
I/O0 2048 64 I/O7
64 pages = 1 block 1Gb device 64K pages 1024 blocks
512Mb device 32K pages 512 blocks 2112 Bytes
8 I/O for x8 16I/O for x16
A page consists of 2112 Bytes in which 2048 Bytes are used for main memory storage and 64 Bytes are for redundancy or for other uses. 1 page = 2112 Bytes 1 block = 2112 Bytes x 64 pages = (128K + 4K) Bytes 1Gb density = 2112 Bytes x 64 pages x 1024 blocks Table 10.1 shows a summary of the addressing for the memory array components. Table 10.1 Memory Addressing Key
Row Address Column Address Main Colum n Addres s A8:A0 A7:A0 A8:A0 A7:A0 Spare Colum n Addres s A3:A0 A2:A0 A3:A0 A2:A0
Density 1 Gb 1 Gb 512 Mb 512 Mb
Bus Width x8 x16 x8 x16
Block Addres s A27:A18 A26:A17 A26:A18 A25:A17
Page Address in Block A17:A12 A16:A11 A17:A12 A16:A11
Main/Spare Area A11 (0=Main, 1=Spare) A10 (0=Main, 1=Spare) A11 (0=Main, 1=Spare) A10 (0=Main, 1=Spare)
Main Page Segment A10:A9 A9:A8 A10:A9 A9:A8
Spare Page Segment A5:A4 A4:A3 A5:A4 A4:A3
Blocks 1024 1024 512 512
An address is read through the I/O port over four consecutive clock cycles, as shown in Table 10.2 and Table 10.3. The Notes for Table 10.2 and Table 10.3 are listed below Table 10.3. Table 10.2 (1Gb) x 8 device
1Gbit 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle I/O0 A0 A8 A12 A20 I/O1 A1 A9 A13 A21 I/O2 A2 A10 A14 A22 I/O3 A3 A11 A15 A23 I/O4 A4 L (Note 1) A16 A24 I/O5 A5 L (Note 1) A17 A25 I/O6 A6 L (Note 1) A18 A26 I/O7 A7 L (Note 1) A19 A27
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
23
Data
Sheet
(Preliminary)
Table 10.3 (512Mb) x8 Addressing
512Mb 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle I/O0 A0 A8 A12 A20 I/O1 A1 A9 A13 A21 I/O2 A2 A10 A14 A22 I/O3 A3 A11 A15 A23 I/O4 A4 L (Note 1) A16 A24 I/O5 A5 L (Note 1) A17 A25 I/O6 A6 L (Note 1) A18 A26 I/O7 A7 L (Note 1) A19 L (Note 1)
Notes: 1. L = VIL. 2. A0 to A11:Column address (12 bits for 2,112 Bytes). A12 to A27: Row address, consists of: A12 to A17: Page address in block (6 bits for 64 pages). 3. A18 to A27: Block address (1 Gb device: A18 to A27, 10 bits for 1024 blocks; 512Mb device: A18 to A26, 9 bits for 512 blocks.)
Table 10.4 (1Gb) x 16 Addressing
1Gb 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle I/O0 A0 A8 A11 A19 I/O1 A1 A9 A12 A20 I/O2 A2 A10 A13 A21 I/O3 A3 L (Note 1) A14 A22 I/O4 A4 L (Note 1) A15 A23 I/O5 A5 L (Note 1) A16 A24 I/O6 A6 L (Note 1) A17 A25 I/O7 A7 L (Note 1) A18 A26 I/O8 - I/O15 L (Note 1) L (Note 1) L (Note 1) L (Note 1)
Table 10.5 (512) x 16 Addressing
512Mb 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle Notes: 1. L = VIL. 2. A0 to A10:Column address (11 bits for 1,056 words) 3. A11 to A26: Row address, consists of: A11 to A16: Page address in block (6 bits for 64 pages). A17 to A26: Block address (1 Gb device: A17 to A26: 10 bits for 1024 blocks; 512Mb device: A17 to A25: 9 bits for 512 blocks.) I/O0 A0 A8 A11 A19 I/O1 A1 A9 A12 A20 I/O2 A2 A10 A13 A21 I/O3 A3 L (Note 1) A14 A22 I/O4 A4 L (Note 1) A15 A23 I/O5 A5 L (Note 1) A16 A24 I/O6 A6 L (Note 1) A17 A25 I/O7 A7 L (Note 1) A18 L (Note 1) I/O8 - I/O15 L (Note 1) L (Note 1) L (Note 1) L (Note 1)
24
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
11. Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read, and Reset are controlled by the thirteen different command operations shown in Table 11.2 on page 25. Address input, command input and data input/output are controlled by the CLE, ALE, CE#, WE#, RE# and WP# signals, as shown in Table 11.1. Table 11.1 Operation Table
CLE H L L L H L L X X X X ALE L H L L L H L X X X X CE# L L X L L L L X X X H X X X X H H H H H X X X X WE# RE# H H H PRE X X X X X X X X X X 0 V/VCC WP# X Read Mode X X X H Program Mode H H H H L 0 V/VCC Data Input During Program (Busy) During Erase (Busy) Write Protect Stand-by Address Input (4 clock cycles) During Read (Busy) Sequential Read & Data Output Command Input Address Input (4 clock cycles) Mode Command Input
Notes: 1. H: VIH, L: VIL, X: VIH or VIL 2. WP# should be biased to CMOS high or CMOS low for standby.
Table 11.2 Command Table
Function Page Read Partial Page Read Read for Page Duplicate ID Read Page Program Cache Program Page Duplicate Program Data Input for Column Address Change Read for Column Address Change Block Erase Reset Status Read 1st Cycle 00h 00h 00h 90h 80h 80h 85h 85h 05h 60h FFh 70h 2nd Cycle 30h 31h 35h -- 10h 15h 10h -- E0h D0h -- -- Command Accepted During Busy State No No No No No No No No No No Yes Yes
Notes: 1. Random Data Input/Output can be executed in a page or 1/4 page. 2. Input of a command other than those specified in Table 11.2 is prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle. 3. During the Busy state, input commands are restricted to 70h and FFh.
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
25
Data
Sheet
(Preliminary)
Table 11.3 Read Mode Operation Status
Operation Output Select Output Deselect Standby Notes: 1. H = VIH 2. L = VIL 3. X = VIH or VIL CLE L L X ALE L L X CE# L X H WE# H H X RE# L H X I/O0 to I/O15 Data Output High Impedance High Impedance Power Active Active Standby
12. Device Operation
12.1 Read Mode
There are two types of read operations: random read and serial page read. The device defaults to Read mode after power-up or a Reset or may be initiated by writing 00h-30h to the command register along with four address cycles. A partial page read may be initiated by writing 00h-31h to the command register along with the four address cycles. The random data read is enabled by a page or partial page address change. The addressed page of data is loaded into the page register and the completion of the loading process is detected by polling the RY/BY# pin or reading the status register. Once the data is loaded into the page register, it may be read by clocking RE#. The high to low transition of the RE# signal outputs data sequentially, starting with the first selected column address and ending with the last selected column address. Subsequent reads will output the last column address data. See Figure 12.1 for timing details. The device may output random data in a page instead of the consecutive sequential data upon entering the random data output command. The column address of the next data to be read can be changed to the address which follows the random data output command. The random data output command may be issued multiple times, but must be within the same page. Figure 12.1 Read Mode
CLE CE# WE#
ALE RE# RY/BY# I/O 00h Start-address input A Select page P x8: n=2112 Bytes x16: n=1056 Words Cell array n Busy 30h A A+1 A+2
Column Address A Page Address P
Page Address P
A data transfer operation from the cell array to the page buffer starts on the rising edge of WE# in the 30h command input cycle (after the address information has been latched). The device is in Busy state during this transfer period. After the transfer period the device returns to Ready state. Serial data can be output synchronously with the RE# clock from the start pointer designated in the address input cycle.
26
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
Figure 12.2 Column Address Read
CLE CE#
WE#
ALE
RE#
RY/BY#
Busy Col. A
I/O
00h
30h
A
A+1 A+2 A+3
05h
E 0h
A'
A'+1 A'+2 A'+3 A'+4
Col. A
Page P
Page P S tart from Col. A A'
Col. A' S tart from Col. A'
Page A
S tart-address input A
Select page P Cell array
During the serial data output from the register the column address can be changed by inputting a new column address using the 05h and E0 commands. The data is read out in serial starting at the new column address. Random column address Change operation can be done multiple times within the same page.
12.2
Page Program
The device conducts an Automatic Page Program operation when it receives a 10h Program confirm command after the address and data are input. The sequence of command and address and data input is shown below. (See Figure 12.3.) Partial page programming is allowed for this device. A page is divisible into eight segments and each segment may be programmed individually or in any combination of segments simultaneously. For example, in x8 devices the first data segment of 512 bytes and the first spare area segment of 16 bytes, are programmable at the same time. Table 12.1 describes the page segments: Table 12.1 Page Segments
x8 Data Area 1st segment 2nd segment 3rd segment 4th segment Spare Area 1st segment 2nd segment 3rd segment 4th segment 512 Bytes x 4 Segments / Page Column Address 0 to 511 Column Address 512 to 1023 Column Address 1024 to 1535 Column Address 1536 to 2047 16 Bytes x 4 Segments / Page Column Address 2048 to 2063 Column Address 2064 to 2079 Column Address 2080 to 2095 Column Address 2096 to 2111 x16 512 Bytes x 4 Segments / Page Column Address 0 to 255 Column Address 256 to 511 Column Address 512 to 767 Column Address 768 to 1023 16 Bytes x 4 Segments / Page Column Address 1024 to 1031 Column Address 1032 to 1039 Column Address 1040 to 1047 Column Address 1048 to 1055
The maximum number of consecutive partial page program operations allowed in the same segment is one. Each of the eight segments may be programmed once before a block erase is required and each of the eight segments is independent with respect to the single program operation allowed. The device also supports random data programming within a page by using the random data input command (85h). Random data input requires the command to be entered between column addresses during the page program command cycle. Once the new column address is entered, the system can continue the page
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
27
Data
Sheet
(Preliminary)
program command cycle by entering the page address and the data. The Page Program confirm command (10h) initiates the programming operation. Once the program operation starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the RY/BY# output, or the Status bit (I/O6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit (I/O0) may be verified. The internal write verify detects only errors for 1s that are not successfully programmed to 0s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure 12.3 Page Program
CLE CE#
WE#
ALE
RE#
RY/BY# I/O 80h Din Din Din Din 10h 70h
Col. A Data input
Page P
Data
Program
Read and verification
The data is transferred (programmed) from the page buffer to the selected page on the rising edge of WE# following input of the 10h command. After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached.
Once the Serial Input command 80h is input, the only acceptable commands are the programming commands 10h, 85h or the Reset command FFh. If any other input command is used, the program operation is not performed and the device must be reset. Figure 12.4 Serial Input Command Sequence
80 XXX 10
Note: If XXX is a command other than 10h, 85h, or FFh, the operation does not execute. When this occurs, the reset command (FFH) must be entered to return the device to a valid state.
12.3
Cache Program
Cache Program is a double buffer scheme for faster programming. The Cache buffer size is identical to the page buffer size (i.e. 2112Byte (x8) or 1056Word (x16) data registers). Data may be written into the cache register while other data stored in the page buffer are programmed into the memory array. After writing the first set of data up to 2112Byte (x8) or 1056Word (x16) into the cache register, the Cache program command (15h) must be entered instead of the standard Page Program command (10h) in order to free up the cache register and start the internal program operation. To transfer data from the cache register to the data register, the device remains in the Busy state for a short period of time (tCBSY) and has its cache register ready for the next data-input while the internal programming starts with the data loaded into the data
28
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
register. The Read Status command (70h) may be issued to verify that the cache register is ready by polling the Cache-Busy status bit (I/O6). Pass/Fail status of the previous page is available upon the return to the Ready state. When the next set of data is input with the Cache Program command, tCBSY is affected by the progress of pending internal programming. The programming of the cache register is initiated only when the pending program cycle is finished and the data register is available for the transfer of data from the cache register. The status bit (I/O5) for internal Ready/Busy may be polled to identify the completion of internal programming. If the system monitors the progress of programming with RY/BY# only, the last page of the target programming sequence must be programmed with Page Program command (10h). Alternatively, if the last page to be programmed is accomplished using the Cache Program command (15h), status bit (I/O5) must be polled to verify that the last program is actually finished before starting other operations. Following the Cache Program Command (15h), the pass/fail status information is available as follows: 1. I/O1 returns the status of the previous page (when ready or when the I/O6 bit is changing to a 1). 2. I/O0 returns the status of the current page (upon true ready, or when the IO5 bit is changing to a 1). 3. I/O0 and I/O1 may be read together. Figure 12.5 Cache Program
tCBSY1 RY/BY# tCBSY2 tCBSY2 tPROG
80h
Address & Data Input*
15h
80h
Address & Data Input
15h
80h
Address & Data Input Data
15h
80h
Address & Data Input Data
10h
70h
Col Add1,2 & Row Add1,2 Data
Col Add1,2 & Row Add1,2 Data
Col Add1,2 & Row Add1,2
Col Add1,2 & Row Add1,2
tCBSY1 RY/BY#
tCBSY2
tCBSY2
I/Ox
80h
Address & Data Input Data
15h
70h
Status output
80h
Address & Data Input Data
15h
70h
Status output
80h
Address & Data Input Data
15h
Col Add1,2 & Row Add1,2
Col Add1,2 & Row Add1,2
Col Add1,2 & Row Add1,2
tCBSY2
70h
Status output
80h
Address & Data Input Data
15h
70h
Status output
Status output
Col Add1,2 & Row Add1,2 Check I/O1 for pass/fail Check I/O5 for internal ready/busy Check I/O0,1 for pass/fail
Note: Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula: tPROG = Program time of last page + program time of the (last -1) page - (program command time + data loading time of last page).
12.4
Page Duplicate Program
The Page Duplicate program is configured to quickly and efficiently rewrite data stored in one full page (no partial page) without utilizing an external memory. Since the time-consuming serial access and re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the block also needs to be copied to the newly assigned free block. A Page Duplicate program operation is performed by first initiating a read operation with command 35h and the address of the source which then duplicates the whole 2112Byte (x8) or 1056Word (x16) data into the internal data buffer. As soon as the device is ready, the Program Confirm command (10h) is required to actually begin the programming operation to the address of the destination page. Once the Page Duplicate Program is finished, any additional partial page programming into the copied pages is prohibited before erasure. The data input cycle for modifying a portion or multiple distant portions of the source page is allowed as shown in Figure 12.6 on page 30. Page data duplicates directly to another Page in a Block.
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
29
Data
Sheet
(Preliminary)
Figure 12.6 Page Duplicate Program Operation
RY/BY# tR tPROG
I/Ox
00h
Add.(4Cycles)
35h
85h
Add.(4Cycles) Destination Address
10h
70h
I/O0
Pass
Col. Add1,2 & Row Add1,2 Source Address
Col. Add1,2 & Row Add1,2 Fail
Figure 12.7 Page Duplicate Program Operation with Random Data Input
RY/BY# tR tPROG
I/Ox
00h
Add.(4Cycles)
35h
85h
Add.(4Cycles)
Data
85h
Add.(2Cycles)
Data
10h
70h
Col. Add1,2 & Row Add1,2 Source Address
Col. Add1,2 & Row Add1,2 Destination Address
Col Add1,2 There is no limitation for the number of repetition.
12.5
Block Erase
The Block Erase process starts with the block erase setup command 60h, followed by two cycles of row address, followed by the block erase execute command D0h. Note that the page address part of the row address is ignored. The Block Erase operation starts on the rising edge of WE# after the Erase Start command D0h which follows the Erase Setup command 60h. This two-cycle process for Erase operations acts as an extra layer of protection from accidental erasure of data due to external noise. The device automatically executes the Erase and Verify operations. Figure 12.8 Block Erase
60 Block Address input: 2 cycles D0 Erase Status command Busy 70 Status Read command I/O Pass
Fail
RY/BY#
12.6
Write Operation Status
The device provides a RY/BY# output pin and Status Register bits to determine the status of a write operation. The status register bits can be used to determine which stage the write operation is in.
12.7
Status Read
The device contains a Status Register which may be read to find out whether a program or erase operation is completed, and whether the program or erase operation completed successfully. After writing a 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE# or RE#, whichever occurs last. The control by two lines allows the system to poll the progress of each device in multiple device connection even if the RY/BY# pins are common wired. RE# or CE# does not have to be toggled for update status. Refer to Table 12.2 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued. Therefore, if the status register is read during a random read cycle, the read command (00h) should be given before starting read cycles. The Status Register clears after another valid command is entered, excluding a status read. An application example with multiple devices is shown in Figure 12.9.
30
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
Table 12.2 Status Output Table
I/O I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 During Program or Erase Operation Reserved Reserved Reserved Reserved Reserved Busy Busy Reserved Page Program Pass/Fail Reserved Normal Reserved Reserved True Ready/Busy Cache Ready/Busy Write Protect Block Erase Pass/Fail Reserved Normal Reserved Reserved Ready/Busy Ready/Busy Write Protect Cache Program Pass/Fail(N) Pass/Fail(N-1) Normal Reserved Reserved True Ready/Busy Cache Ready/Busy Write Protect Read Reserved Reserved Normal Reserved Reserved Ready/Busy Ready/Busy Write Protect 0 = Busy; 1 = Ready 0 = Busy; 1 = Ready 0 = Protected; 1 = Unprotected Definition 0 = Pass; 1 = Fail 0 = Pass; 1 = Fail 0 = Normal
Notes: 1. True Ready/Busy represents internal program operation status which is being executed in cache program mode. 2. I/Os defined `Not use' are recommended to be masked out when Read Status in being executed.
Figure 12.9 Multiple Devices
CE(1)# ALE CLE WE# RE# CE(2)# CE(N)#
Device(1)
Device(2)
Device(N)
n I/On RY/BY#
If the RY/BY# pin signals from multiple devices are wired together as shown in Figure 12.9, the Status Read function can be used to determine the status of each individual device. Figure 12.10 Status Read Timing Application Example
RY/BY# CLE ALE WE# CE1# CEN# RE# I/O 70H 70H Status on Device 1 Status on Device N VIL Busy
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
31
Data
Sheet
(Preliminary)
12.8
Reset
The Reset mode aborts all operations in progress including read, erase and program. For example, in the case of a Program or Erase operation the internally generated voltage is discharged to 0 volts and the device enters standby. Any attempted memory data alteration is invalidated if interrupted by a reset command. The response to an FFh Reset command input during the various device operations is shown in Figure 12.11 to Figure 12.15. Figure 12.11 Reset (FFh) Command Input During Programming
80 Internal VPP 10 FF 00
RY/BY#
Note: The reset time (tRST) is not the same for program, erase, and read operations.
tRST (see Note)
Figure 12.12 Reset (FFh) Command Input During Erasing
Internal erase voltage D0 FF 00
RY/BY# tRST (see Note)
Note: The reset time (tRST) is not the same for program, erase, and read operations.
Figure 12.13 Reset (FFh) Command Input During a Read Operation
00 RY/BY# FF 00
tRST (see Note)
Note: The reset time (tRST) is not the same for program, erase, and read operations.
Figure 12.14 Reset (FFh) Command During Operations Other Than Program, Erase, or Read
00 RY/BY# FF 00
tRST (see Note)
Note: The reset time (tRST) is not the same for program, erase, and read operations.
32
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
Figure 12.15 Status Read Command (70h) Input After a Reset
FF 70 I/O status: Ready/Busy Ready
RY/BY#
FF
70
I/O status: Ready/Busy
Busy
RY/BY#
13. Application Notes
13.1 Power On/Off Sequence and Power-On Read Enable
Power-On/Off Sequence
The WP# signal is useful for protecting against data corruption at power-on/off. The following timing sequence is necessary. The WP# signal may be negated any time after the VCC reaches 1.6 V and the CE# signal is kept high in power up sequence. A reset command issued during the power up sequence is ignored. Figure 13.1 Power-On/Off Sequence
1.7 V 1.6 V 1.7 V 1.6 V
13.1.1
0V
V CC
CE# RE# CLE, ALE
Don't Care
Don't Care
WP# Don't Care tPRE 10 s Operation
Don't Care WE#
Don't Care
Don't Care
RY/BY#
For stable operation, it is recommended to start accessing the device 200 s after VCC becomes 1.6 V. There is no restriction regarding the VCC ramp rate.
13.1.2
Power-On Read Enable
Power on read is a feature for certain architectures that requires the system to read data from page 0 without a command sequence on power-up. To enable power on read, PRE must be tied to VCC to ensure a simultaneous ramp rate. Please refer to the following waveform. Page zero data is read from the memory array to the page buffer without any command and address input sequence following power-on. The function will be performed when VCC attains about 1.6 V. The PRE pin controls activation of auto-page read function.
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
33
Data
Sheet
(Preliminary)
Serial access may begin after tRPRE. A reset command issued during the power-on read enable is acceptable. Figure 13.2 shows the timing diagram. Figure 13.2 Power-On Auto-read Enable
1.7 V 1.6 V 1.7 V 1.6 V
0V
V CC
CE# RE# CLE, ALE
Don't Care
Don't Care
WP# Don't Care tRPRE 10 s Operation
Don't Care WE#
Don't Care
Don't Care
RY/BY#
PRE#
13.2
Status Read During a Read Operation
Figure 13.3 Status Read During a Read Operation
00 30 [A]
command CE#
00
70
WE# BY# RY/
RE# Address N
2nd Cycle of Status Read the Read Command command input Status Read
Data output
The device status can be read by inputting the Status Read command 70h in Read mode. Once the device is set to Status Read mode by a 70h command, the device will not return to Read mode. However, when the Read command 00h is input during [A], the Status mode is reset and the device returns to Read mode. In this case, data output starts automatically from address N and address input is unnecessary. A pull-up resistor must be used for termination because the RY/BY# buffer consists of an open drain circuit.
34
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
Figure 13.4 RY/BY#: Termination for the Ready/Busy Pin (RY/BY#)
VCC VCC Device CL VSS
R= = VCC max - VOL IOL + IL 1.95 V 3 mA + IL
Read y
R RY/BY#
V CC VOL tf
VOL=0.1V, VOH= VCC - 0.1V VOH Busy VOL tr
This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value.
13.2.1
When WP# Signal Goes Low
Holding the WP# pin low protects the device during power transitions. If WP# is low during the program/erase command input period, the device is protected and does not enter the program/erase operation. If WP# is high during the program/erase command input period, the device can execute the program/erase operation. The user should keep the WP# pin either high or low during the complete command & program/erase operation. The operations are enabled and disabled as shown in the following timing diagrams:
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
35
Data
Sheet
(Preliminary)
Figure 13.5 WP# Signal--Low
[Enable Programming]
WE#
DIN
80
10
WP#
RY/ BY#
tWW (100 ns min) [Disable Programming]
WE#
DIN
80
10
WP#
RY/ BY#
tWW (100 ns min) [Enable Erasing]
WE#
DIN
60
D0
WP#
RY/ BY#
tWW (100 ns min) [Disable Erasing]
WE#
DIN
60
D0
WP#
RY/ BY#
tWW (100 ns min)
36
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
13.2.2
CE# Don't Care Feature
CE# does not need to be continuously asserted across command and address write operations or during busy periods as was required by some earlier generation NAND interface devices.
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
37
Data
Sheet
(Preliminary)
14. Revision History
Section Revision A (January 3, 2005) Initial release Revision A1 (May 16, 2005) Performance Characteristics table Program and Erase Performance table Connection Diagrams Block Diagram DC Characteristics table AC Characteristics and Recommended Operating Conditions table Program and Erase Characteristics table ID Definition table x8 Array Organization x16 Array Organization When WP# Signal Goes Low Revision A2 (July 6, 2005) Front Page Ordering Information DC Characteristics Table AC Characteristics Table Program and Erase Characteristics Table Byte Tables Pin Names Command Table Pipeline Read Reset After Power-on Timing Diagrams Capacitance Table Valid Blocks Table Power-on Read Enable Revision A3 (September 12, 2005) Title Connection Diagrams Program and Erase Characteristics Distinctive Characteristics Schematic Cell Layout and Address Assignment Format Spansion Xtreme Mode Revision A4 (November 11, 2005) Added ECC-free Updated entire diagram Changed various program and erase specifications Changed data retention value Added the Memory Addressing Key table Converted Data Sheet to Standard Format Updated and Added Content Added 100% Valid Blocks statement Revised and corrected various parameters Added model numbers 02 and 03 Removed Industrial temperature grade Revised various parameters Revised and added various timing parameters Revised tCBSY1 and tCBSY2 Corrected P/E Specification Removed 7th ID Byte table Updated Device ID Bytes 2, 3, 4, and 5 Removed VIO pin Removed RY/BY#1 and RY/BY#2 Added Pipeline Read--Full Page no additional requests command Revised feature description and timing diagram Removed section Corrected multiple timing diagrams Updated the entire table Updated the entire table Added Section and timing diagrams Updated specifications. Updated entire table Updated all diagrams Corrected the RY/BY# command Added standard and low power mode specifications to: ICC4 and ICC5 Updated Min. specifications for: tWP, tDS, and tDH Updated entire table Updated entire table
Updated the figure
Description
Updated the figure Updated section
38
S30MS-P ORNANDTM Flash Family
S30MS-P_00_A7 August 4, 2006
Data
Sheet
(Preliminary)
Section Global Distinctive Characteristics Status Read Output table Reset Timing Diagrams Power On/Off Sequence Revision A5 (December 16, 2005) Valid Blocks Table DC Characteristics Serial Read Cycle Timing Diagram Revision A6 (March 22, 2006) Xtreme Mode Command Definitions Ordering Revisions Programming Program and Erase Characteristics AC Characteristics Power on Read Enable Revision A7 (August 4, 2006) Global Performance Characteristics Connection Diagrams Capacitance Valid Blocks DC Characteristics AC Characteristics Program and Erase Characteristics Timing Diagrams Ordering Information Colophon Removed all references to Xtreme Mode Updated tables Updated diagram Updated Table Removed specifications Removed 2 Gb specifications Changed write performance value Updated table Changed the tRST values Updated section
Description
Removed the specifications for low power mode Corrected Reset Pin Signal
Defined WP# State during Block Status Read Added Model Number descriptions to include boot block product Clarified notes on Program/Erase Characteristics table Changed the Dummy Busy Time During Cache Programming Changed the timing for Partial Page Data Transfer to Memory Cell Array to Register (tR) Clarified Power on Read Operation
Added the Capacitance Values for WP# and CE# pins Updated table Changed ICC4 and ICC5 Changed Read Cycle Timing Parameters Changed Timing for Command Latch Enable and Address Latch Enable Updated table Corrected Page Transfer Timing on Page Duplicate Program Timing Diagram Update Models Numbers for parts that require ECC
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
August 4, 2006 S30MS-P_00_A7
S30MS-P ORNANDTM Flash Family
39

▲Up To Search▲

Price & Availability of S30MS01GP25TAW002

	To Download S30MS01GP25TAW002 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .